Runtime assurance from signal temporal logic safety specifications

L. Baird, S. Coogan
American Control Conference, 2023


In this paper, we propose a runtime assurance mechanism for online verification of a control system given a signal temporal logic (STL) specification that, at each time step, must hold for the remaining state trajectory. Given a nominal control input, we propose a mechanism that minimally adjusts the input at each time step in order to ensure existence of future inputs that maintain satisfaction of the STL specification. Because STL constraints generally impose requirements on future states, the runtime assurance mechanism also enforces continued satisfaction of the STL constraint evaluated at all past time steps. Lastly, to ensure a feasible input is always available, we provide a novel characterization of a persistently feasible set and require that the system state is always able to reach this set. We formulate this approach as a mixed integer convex program and demonstrate it on examples.